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Intel(R) 80321 I/O Processor
Datasheet
Product Features
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Core Features -- Integrated Intel(R) XScaleTM Core -- ARM* V5T Instruction Set -- ARM V5E DSP Extensions -- 400 MHz and 600 MHz -- Write Buffer, Write-back Cache PCI Bus Interface -- PCI Local Bus Specification, Rev. 2.2 compliant -- PCI-X Addendum to the PCI Local Bus Specification, Rev. 1.0a -- 64-bit/66MHz Operation in PCI Mode --64-bit/133MHz Operation in PCI-X Mode -- Support 32-bit PCI Initiators and Targets -- Four Split Read Requests as Initiator -- Eight Split Read Requests as Target -- 64-bit Addressing Support Memory Controller --PC200 Double Data Rate (DDR) SDRAM -- Up to 1 GB of 64-bit DDR SDRAM -- Up to 512 MB of 32-bit DDR SDRAM -- Single-bit Error Correction, Multi-bit Support (ECC) -- 1024-byte Posted Memory Write Queue -- 40- and 72-bit wide Memory Interface Address Translation Unit -- 2 KB or 4 KB Outbound Read Queue -- 4 KB Outbound Write Queue -- 4 KB Inbound Read and Write Queue --Connects Internal Bus to PCI/PCI-X Bus
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DMA Controller -- Two Independent Channels Connected to Internal Bus -- Up to 1064 MB/s Burst Support in PCI-X Mode -- Up to 1600 MB/s Burst Support for Internal Bus -- Two 1-KB Queues in Ch-0 and Ch-1 -- 232 Addressing Range on Internal Bus Interface -- 264 Addressing Range on PCI Interface Application Accelerator Unit -- Performs XOR on Read Data -- Compute Parity Across Local Memory Blocks -- 1 KB/512-byte Store Queue I2C Bus Interface Units -- Two Separate I2C Units -- Serial Bus -- Master/Slave Capabilities -- System Management Functions SSP Serial Port -- Full-duplex Synchronous Serial Interface -- Supports 7.2 KHz to 1.84 MHz Bit Rates Peripheral Performance Monitoring Unit -- One Dedicated Global Time Stamp Counter -- Fourteen Programmable Event Counters -- Three Control/Status Registers Timers -- Two Dual-programmable 32-bit Timers -- Watchdog Timer 544-Ball, Plastic Ball Grid Array (PBGA) Eight General Purpose I/O Pins
Document Number: 273518-002 June 2002
Intel(R) 80321 I/O Processor
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. The Intel(R) Intel(R) 80321 I/O Processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Intel(R) internal code names are subject to change. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Copyright(c) Intel Corporation, 2002 AlertVIEW, i960, AnyPoint, AppChoice, BoardWatch, BunnyPeople, CablePort, Celeron, Chips, Commerce Cart, CT Connect, CT Media, Dialogic, DM3, EtherExpress, ETOX, FlashFile, GatherRound, i386, i486, iCat, iCOMP, Insight960, InstantIP, Intel, Intel logo, Intel386, Intel486, Intel740, IntelDX2, IntelDX4, IntelSX2, Intel ChatPad, Intel Create&Share, Intel Dot.Station, Intel GigaBlade, Intel InBusiness, Intel Inside, Intel Inside logo, Intel NetBurst, Intel NetStructure, Intel Play, Intel Play logo, Intel Pocket Concert, Intel SingleDriver, Intel SpeedStep, Intel StrataFlash, Intel TeamStation, Intel WebOutfitter, Intel Xeon, Intel XScale, Itanium, JobAnalyst, LANDesk, LanRover, MCS, MMX, MMX logo, NetPort, NetportExpress, Optimizer logo, OverDrive, Paragon, PC Dads, PC Parents, Pentium, Pentium II Xeon, Pentium III Xeon, Performance at Your Command, ProShare, RemoteExpress, Screamline, Shiva, SmartDie, Solutions960, Sound Mark, StorageExpress, The Computer Inside, The Journey Inside, This Way In, TokenExpress, Trillium, Vivonic, and VTune are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others.
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Intel(R) 80321 I/O Processor
Contents
1.0 Introduction......................................................................................................................... 7 1.1 About This Document............................................................................................7 1.1.1 Terminology..............................................................................................7 1.1.2 Other Relevant Documents ...................................................................... 8 About the Intel(R) 80321 I/O Processor ................................................................... 9
1.2 2.0
Features ...........................................................................................................................11 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 Internal Bus ......................................................................................................... 11 DMA Controller.................................................................................................... 11 Address Translation Unit .....................................................................................12 Messaging Unit.................................................................................................... 12 Memory Controller............................................................................................... 12 Peripheral Bus Interface...................................................................................... 12 Application Accelerator Unit ................................................................................ 13 Performance Monitoring Unit............................................................................... 13 I2C Bus Interface Units ........................................................................................ 13 Synchronous Serial Port Unit ..............................................................................13
3.0
Package Information ........................................................................................................14 3.1 Package Introduction........................................................................................... 14 3.1.1 Functional Signal Definitions ..................................................................14 3.1.2 544-Lead PBGA Package ...................................................................... 25 Package Thermal Specifications .........................................................................39 3.2.1 Thermal Specifications ........................................................................... 39 3.2.1.1 Ambient Temperature................................................................ 39 3.2.1.2 Case Temperature .................................................................... 39 3.2.1.3 Thermal Resistance ..................................................................39 3.2.2 Thermal Analysis .................................................................................... 40 Socket Information .............................................................................................. 41 3.3.1 Socket-Header Vendor........................................................................... 41 3.3.2 Burn-in Socket Vendor ........................................................................... 41 3.3.3 Shipping Tray Vendor............................................................................. 41 3.3.4 Logic Analyzer Interposer Vendor .......................................................... 41 3.3.5 JTAG Emulator Vendor .......................................................................... 42
3.2
3.3
4.0
Electrical Specifications.................................................................................................... 43 4.1 4.2 4.3 4.4 Absolute Maximum Ratings................................................................................. 43 VCCPLL Pin Requirements ................................................................................... 43 Targeted DC Specifications................................................................................. 44 Targeted AC Specifications................................................................................. 46 4.4.1 Clock Signal Timings ..............................................................................46 4.4.2 PCI Interface Signal Timings ..................................................................47 4.4.3 DDR SDRAM Interface Signal Timings .................................................. 48 4.4.4 Peripheral Bus Interface Signal Timings ................................................ 48 4.4.5 I2C Interface Signal Timings................................................................... 48 4.4.6 SSP Interface Signal Timings................................................................. 49 4.4.7 Boundary Scan Test Signal Timings ...................................................... 50 AC Timing Waveforms ........................................................................................ 51 AC Test Conditions ............................................................................................. 55 June 2002 3
4.5 4.6 Datasheet
Intel(R) 80321 I/O Processor
Figures
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Intel(R) 80321 I/O Processor Functional Block Diagram ....................................... 10 544-Lead PBGA Package (Top View)................................................................. 25 544-Lead PBGA Package (Bottom View) ........................................................... 26 Ball Map - Left Side - Top View........................................................................... 27 Ball Map - Right Side - Top View ........................................................................ 28 Thermocouple Attachment - No Heatsink ........................................................... 39 VCCPLL Lowpass Filter ........................................................................................ 43 Clock Timing Measurement Waveforms ............................................................. 51 Output Timing Measurement Waveforms ........................................................... 51 Input Timing Measurement Waveforms .............................................................. 52 I2C Interface Signal Timings................................................................................ 52 DDR SDRAM Write Timings ............................................................................... 53 DDR SDRAM Read Timings ............................................................................... 54 AC Test Load for all Signals Except PCI and DDR SDRAM ............................... 55 PCI/PCI-X TOV(max) Rising Edge AC Test Load............................................... 55 PCI/PCI-X TOV(max) Falling Edge AC Test Load .............................................. 55 PCI/PCI-X TOV(min) AC Test Load .................................................................... 56
Tables
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Related Documentation......................................................................................... 8 Pin Description Nomenclature............................................................................. 14 DDR SDRAM Signals.......................................................................................... 15 Peripheral Bus Interface Signals ......................................................................... 16 PCI Bus Signals .................................................................................................. 19 Serial Port Interface Signals................................................................................ 20 Miscellaneous Signals......................................................................................... 21 Pin Mode Behavior .............................................................................................. 23 544-Lead PBGA Package - Alphabetical Ball Listing .......................................... 29 544-Lead PBGA Package - Alphabetical Signal Listing ...................................... 34 544-Lead PBGA Package Thermal Characteristics ............................................ 40 Socket-Header Vendor........................................................................................ 41 Burn-in Socket Vendor ........................................................................................ 41 Shipping Tray Vendor ......................................................................................... 41 Logic Analyzer Interposer Vendor ....................................................................... 41 JTAG Emulator Vendor ....................................................................................... 42 Operating Conditions .......................................................................................... 43 DC Characteristics .............................................................................................. 44 ICC Characteristics .............................................................................................. 45 Clock Timings...................................................................................................... 46 PCI Signal Timings.............................................................................................. 47 DDR SDRAM Signal Timings .............................................................................. 48 Peripheral Bus Signal Timings ............................................................................ 48 I2C Signal Timings............................................................................................... 48 SSP Signal Timings ............................................................................................ 49 Boundary Scan Test Signal Timings ................................................................... 50 DAT Mode Timings ............................................................................................. 50 Bypass Mode Timings ......................................................................................... 50 AC Measurement Conditions .............................................................................. 55
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Intel(R) 80321 I/O Processor
Revision History
Date June 2002 February 2002 Revision # 002 001 Description Removed Advance Information designation. Initial release.
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1.0
1.1
Introduction
About This Document
This is the Intel(R) 80321 I/O Processor Datasheet. This datasheet contains a functional overview, package signal locations, targeted electrical specifications, and bus functional waveforms. Detailed functional descriptions other than parametric performance is published in the Intel(R) 80321 I/O Processor Developer's Manual. Intel Corporation assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein. Intel retains the right to make changes to these specifications at any time, without notice. In particular, descriptions of features, timings, packaging, and pin-outs does not imply a commitment to implement them. In fact, this document does not imply a commitment by Intel to design, manufacture, or sell the product described herein.
1.1.1
Terminology
To aid the discussion of the Intel(R) 80321 I/O processor (80321) architecture, the following terminology is used:
Downstream Host processor At or toward a PCI bus with a higher number (after configuration) Processor located upstream from the 80321
Local processor Intel(R) XScaleTM core (ARM* architecture compliant) within the 80321 Local bus Local memory Upstream 80321 Internal Bus Memory subsystem on the Intel(R) XScaleTM core PC200 DDR SDRAM or Peripheral Bus Interface busses At or toward a PCI bus with a lower number (after configuration)
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Intel(R) 80321 I/O Processor Introduction
1.1.2
Table 1.
Other Relevant Documents
Related Documentation
Document Title Document# / Contact 273410 273416 273411 273354 273414 273415 PCI Special Interest Group 1-800-433-5177 http://www.pcisig.com/home
Intel 80312 I/O Companion Chip Developer's Manual Intel 80312 I/O Companion Chip Specification Update Intel(R) 80200 Processor based on Intel(R) XScaleTM Microarchitecture Developer's Manual Intel 80310 I/O Processor Chipset with Intel XScale Intel 80200 Processor based on Intel XScale Intel 80200 Processor based on Intel XScale PCI Local Bus Specification, Revision 2.2 PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a PCI-to-PCI Bridge Architecture Specification, Revision 1.1 PCI System Design Guide, Revision 1.0 PCI Hot-Plug Specification, Revision 1.0 PCI Bus Power Management Interface Specification, Revision 1.1 I2C Peripherals for Microcontrollers Advanced Configuration and Power Interface Specification, Revision 1.0 (ACPI) NOTE: Also see our product website at: http://developer.intel.com/design/iio/.
(R) (R) (R) (R) TM (R) (R) TM (R)
(R)
Microarchitecture Design Guide
Microarchitecture Datasheet Microarchitecture Specification Update
TM
Philips Semiconductor http://www.teleport.com/~acpi/
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Intel(R) 80321 I/O Processor Introduction
1.2
About the Intel(R) 80321 I/O Processor
The 80321 is a single-function device that integrates the Intel(R) XScaleTM core with intelligent peripherals, including a PCI bus application bridge. The 80321 consolidates into a single system:
* * * * * * * * * * *
Intel(R) XScaleTM core PCI - Local Memory Bus Address Translation Unit I2O* Messaging Unit Direct Memory Access (DMA) Controller Peripheral Bus Interface Unit Integrated Memory Controller Performance Monitor Application Accelerator Two I2C Bus Interface Units Synchronous Serial Port Unit Eight General Purpose Input Output (GPIO) ports
It is an integrated processor that addresses the needs of intelligent I/O applications and helps reduce intelligent I/O system costs. The PCI Bus is an industry standard, high performance, low latency system bus. The 80321 PCI Bus is capable of 133 MHz operation in PCI-X mode as defined by the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a. Also, the processor supports a 66 MHz conventional PCI mode as defined by the PCI Local Bus Specification, Revision 2.2. The addition of the Intel(R) XScaleTM core brings intelligence to the PCI bus application bridge. The 80321 is a single-function PCI device. This function represents the address translation unit. The address translation unit is an `application bridge' as defined by the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a. The 80321 contains PCI configuration space accessible through the PCI bus.
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Intel(R) 80321 I/O Processor Introduction
Figure 1 is a block diagram of the 80321. Figure 1. Intel(R) 80321 I/O Processor Functional Block Diagram
72-Bit I/F 32-Bit I/F I2C Serial Bus Serial Bus
Intel(R) XScaleTM Core
DDR I/F Unit
PBI Unit (Flash)
I2C Bus Interface
Application Accelerator
SSP Serial Bus
Internal Bus
Messaging Unit
Address Translation Unit
Two DMA Channels
Performance Monitoring Unit
64-bit / 32-bit PCI Bus
Intel(R) 80321 I/O Processor
Notes: Intel XScale Microarchitecture is ARM* Architecture compliant. * Other brands and names are the property of their respective owners.
A7610-02
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Intel(R) 80321 I/O Processor Features
2.0
Features
The 80321 combines the Intel(R) XScaleTM core with powerful new features to create an intelligent I/O processor. This single-function PCI device is fully compliant with the PCI Local Bus Specification, Revision 2.2. 80321-specific features include:
* * * * *
Address Translation Unit Memory Controller Peripheral Bus Interface Application Accelerator Unit I2C Bus Interface Units
* * * * *
DMA Controller Performance Monitoring Unit Synchronous Serial Port Unit Messaging Unit I2O* Compatibility
The subsections that follow briefly overview each feature. Refer to the appropriate chapter in the Intel(R) 80321 I/O Processor Developer's Manual for full technical descriptions. The 80321 core is based upon the Intel(R) XScaleTM core. The core processor operates at a maximum frequency of 600 MHz. The instruction cache is 32 Kbytes in size and is 32-way set associative. Also, the core processor includes a data cache that is 32 Kbytes and is 32-way set associative and a mini data cache that is 2 Kbytes and is 2-way set associative. The 80321 includes 8 General Purpose I/O (GPIO) pins.
2.1
Internal Bus
The Internal Bus is a high-speed interconnect between all internal units and controllers. The Internal Bus operates at 200 MHz and is 64 bits wide.
2.2
DMA Controller
The DMA Controller allows low-latency, high-throughput data transfers between PCI bus agents and the local memory. Two separate DMA channels accommodate data transfers on the PCI bus. The DMA Controller supports chaining and unaligned data transfers. It is programmable through the Intel(R) XScaleTM core only.
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Intel(R) 80321 I/O Processor Features
2.3
Address Translation Unit
The Address Translation Unit (ATU) allows PCI transactions direct access to the 80321 local memory. The ATU supports transactions between PCI address space and the 80321 address space. Address translation is controlled through programmable registers accessible from both the PCI interface and the Intel(R) XScaleTM core. Dual access to registers allows flexibility in mapping the two address spaces. The ATU also supports the following extended capability configuration headers: 1. Power Management header as defined by PCI Bus Power Management Interface Specification, Revision 1.1. 2. Message Signaled Interrupt capability structure specified in PCI Local Bus Specification, Revision 2.2. 3. PCI-X Capabilities List Item specified in the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a.
2.4
Messaging Unit
The Messaging Unit (MU) provides data transfer between the PCI system and the 80321. It uses interrupts to notify each system when new data arrives. The MU has four messaging mechanisms:
* * * *
Message Registers Doorbell Registers Circular Queues Index Registers
Each allows a host processor or external PCI device and the 80321 to communicate through message passing and interrupt generation.
2.5
Memory Controller
The Memory Controller allows direct control of a PC200 DDR SDRAM memory subsystem. It features programmable chip selects and support for error correction codes (ECC). External memory can be configured as PCI addressable memory or private 80321 memory.
2.6
Peripheral Bus Interface
The Peripheral Bus Interface Unit (PBI) is a data communication path to certain components of a 80321 hardware system that do not have PCI bus interfaces and/or do not optimally reside on the PCI Bus. Examples of such components include Flash Memory and DSP host interface ports. The PBI allows the processor to manipulate data and interact with these components in the I/O environment. To perform these tasks at high bandwidth, the bus features a burst transfer capability which allows successive 32-bit data transfers. The bus has a 33 MHz, 66 MHz and a 100 MHz operating mode.
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2.7
Application Accelerator Unit
The Application Accelerator Unit transfers blocks of data to and from the local memory and performs boolean operations, such as XOR, on the data.
2.8
Performance Monitoring Unit
The Performance Monitoring Unit (PMON) allows various events on the 80321 to be monitored. The 14 Event Counters can be programmed to observe events selected from a pre-defined set of events.
2.9
I2C Bus Interface Units
There are two I2C (Inter-Integrated Circuit) Bus Interface Units that allow the Intel(R) XScaleTM core to serve as a master and slave device residing on the I2C bus. The I2C unit uses a serial bus developed by Philips Semiconductor* consisting of a two-pin interface. The bus allows the 80321 to interface to other I2C peripherals and microcontrollers for system management functions. It requires a minimum of hardware for an economical system to relay status and reliability information on the I/O subsystem to an external device. Also refer to I2C Peripherals for Microcontrollers (Philips Semiconductor*).
2.10
Synchronous Serial Port Unit
The Synchronous Serial Port (SSP) Unit is a full-duplex synchronous serial interface. It can connect to a variety of external analog-to-digital (A/D) converters, audio and telecom codecs, and many other devices which use serial protocols for transferring data. It supports the National Microwire*, Texas Instrument* synchronous serial protocol, and the Motorola* serial peripheral interface (SPI) protocol. The SPI interface can be configured to operate as the Philips Semiconductor I2C interface.
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Intel(R) 80321 I/O Processor Package Information
3.0
3.1
Package Information
Package Introduction
The 80321 is offered in a Plastic Ball Grid Array (PBGA) package. This is a perimeter array package with 508 ball connections in the outer area of the package and a square 6x6 grid of rows of ball connections in the middle area of the package. See Figure 3 "544-Lead PBGA Package (Bottom View)" on page 26.
3.1.1
Functional Signal Definitions
This section defines the pins and signals.
Table 2.
Pin Description Nomenclature
Symbol I O I/O OD Sync(...) Input pin only Output pin only Pin can be either an input or output Open Drain pin Pin must be connected as described Synchronous. Signal meets timings relative to an input clock. Sync(P) Synchronous to P_CLK Sync(M) Synchronous to M_CK[2:0] Sync(PB) Synchronous to PB_CLK Sync(SS) Synchronous to SSCKO Sync(T) Synchronous to TCK Async Rst(P) Rst(M) Rst(T) (Configuration Pin) Asynchronous. Inputs may be asynchronous relative to all clocks. All asynchronous signals are level-sensitive. The pin is reset with P_RST#. The pin is reset with M_RST#. Note that M_RST# is asserted when P_RST# is asserted or PCSR[5] is set with software. The pin is reset with TRST# These pins are used during reset to configure the processor. These pins have internal pullup resisters which are turned on when P_RST# is low. To configure the pin low connect a 4.7K resister from the pin to ground. By default the pin is configured high. Description
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Table 3.
DDR SDRAM Signals
Name RCVENI# RCVENO# M_CK[2:0] M_CK[2:0]# M_RST# SA[12:0] Count 1 1 3 3 1 13 Type I O O O O Async O Sync(M) Rst(M) O Sync(M) Rst(M) O Sync(M) Rst(M) O Sync(M) Rst(M) O Sync(M) Rst(M) O Sync(M) Rst(M) O Sync(M) Rst(M) I/O Sync(M) Rst(M) I/O Sync(M) Rst(M) I/O Sync(M) Rst(M) O Sync(M) Rst(M) I Description RECEIVE ENABLE IN provides delay information for enabling the input receivers and must be connected to RCVENO# of the 80321. RECEIVE ENABLE OUT must be connected to RCVENI# of the 80321 and be trace length matched to Clock Trace plus average DQ Traces. MEMORY CLOCKS are used to provide the positive differential clocks to the external SDRAM memory subsystem. MEMORY CLOCKS are used to provide the negative differential clocks to the external SDRAM memory subsystem. MEMORY RESET indicates when the memory subsystem has been reset with P_RST# or a software reset. MEMORY ADDRESS BUS carries the multiplexed row and column addresses to the SDRAM memory banks. For SA[10], See Note 1. SDRAM BANK ADDRESS indicates which of the SDRAM internal banks are read or written during the current transaction. See Note 1. SDRAM ROW ADDRESS STROBE indicates the presence of a valid row address on the Multiplexed Address Bus SA[12:0]. See Note 1. SDRAM COLUMN ADDRESS STROBE indicates the presence of a valid column address on the Multiplexed Address Bus SA[12:0]. See Note 1. SDRAM WRITE ENABLE indicates that the current memory transaction is a write operation. See Note 1. SDRAM CHIP SELECT enables the SDRAM devices for a memory access (Physical banks 0 and 1). See Note 1. SDRAM CLOCK ENABLE enables the clocks for the SDRAM memory. Deasserting places the SDRAM in self-refresh mode. See Note 1. SDRAM DATA BUS carries 64-bit data to and from memory. During a data cycle, read or write data is present on one or more contiguous bytes. During write operations, unused pins are driven to determinate values. See Note 1. SDRAM ECC CHECK BITS carry the 8-bit ECC code to and from memory during data cycles. See Note 1. SDRAM DATA STROBES carry the strobe signals which are used to capture data on the data bus. See Note 1. SDRAM DATA MASK controls which bytes on the data bus should be written. When SDQM[8:0] is asserted, the SDRAM devices do not accept valid data from the byte lanes. See Note 1. SDRAM VOLTAGE REFERENCE is used to supply the reference voltage to the differential inputs of the memory controller pins.
SBA[1:0]
2
SRAS#
1
SCAS#
1
SWE#
1
SCE[1:0]#
2
SCKE[1:0]
2
DQ[63:0]
64
SCB[7:0]
8
DQS[8:0]
9
SDQM[8:0]
9
VREF
1
NOTE: 1. These pins remain functional for 20 M_CK[2:0] periods after M_RST# is asserted for a warm boot. The designated Rst(M) state applies after 20 M_CK[2:0] periods after M_RST# is asserted. For more details, refer to the MCU Chapter of the Intel(R) 80321 I/O Processor Developer's Manual.
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Intel(R) 80321 I/O Processor Package Information
Table 4.
Peripheral Bus Interface Signals (Sheet 1 of 3)
Name AD[31:0] Count 32 Type Description
I/O ADDRESS / DATA BUS During an address cycle bits 31-2 contain the Sync(PB) physical word address and bits 1-0 specify the number of data transfers Rst(M) during the bus transaction. 00= 1 Transfer 01= 2 Transfers 10= 3 Transfers 11= 4 Transfers. During a data cycle bits 31-0, 15-0 or 7-0 contain valid data, depending on the corresponding 32-, 16- or 8-bit bus width. During 16- and 8-bit bus write operations the unused bus pins are driven to determinate values.
A[3:2]
2
ADDRESS [3:2] carries a demultiplexed version of bits 3 and 2 of the O Sync(PB) address bus. During an address cycle A[3:2] matches AD[3:2]. During a Rst(M) bursted read or write data cycle A[3:2] represents the current DWORD address in the bursted transaction. O BYTE ENABLES select which of up to four data bytes on the bus Sync(PB) participate in the current bus access. The byte enables are asserted Rst(M) during the address cycle. These signals do not toggle during a burst and they remain active through the last data cycle. Byte enable encoding is dependent on the bus width: 32-bit bus: * BE[3]# enables data on AD[31:24] * BE[2]# enables data on AD[23:16] * BE[1]# enables data on AD[15:8] * BE[0]# enables data on AD[7:0] 16-bit bus: * BE[3]# enables data on AD[15:8] * BE[2]# is not used (state is high) * BE[1]# becomes Address Bit 1 (A[1]) * BE[0]# enables data on AD[7:0] 8-bit bus: * BE[3]# is not used (state is high) * BE[2]# is not used (state is high) * BE[1]# becomes Address Bit 1 (A[1]) * BE[0]# becomes Address Bit 0 (A[0]) For 16- and 8-bit bus accesses these address bits are asserted in conjunction with A[3:2].
BE[3:0]#
4
ALE
1
O ADDRESS LATCH ENABLE indicates the transfer of a physical address. Sync(PB) The pin is asserted during the first address cycle and deasserted during Rst(M) the second address cycle. The pin floats whenever the bus is relinquished to an external device O ADDRESS STROBE indicates a valid address and the start of a new bus Sync(PB) access. The pin is asserted during the second address cycle and Rst(M) deasserted during the first data cycle. The pin floats whenever the bus is relinquished to an external device O PERIPHERAL BUS CLOCK is the reference clock for all signals on the peripheral bus.
ADS#
1
PB_CLK W/R#
1 1
O WRITE / READ indicates whether the bus access is a write or a read with Sync(PB) respect to the 80321 and is valid during the entire bus access. This pin Rst(M) can be used to control the OE# input on the flash ROM. The pin floats whenever the bus is relinquished to an external device 0 = read 1 = write
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Table 4.
Peripheral Bus Interface Signals (Sheet 2 of 3)
Name FWE# Count 1 Type Description
O FLASH WRITE ENABLE indicates whether the bus access is a write or a Sync(PB) read with respect to the 80321 and is valid during the entire bus access. Rst(M) This pin is used for flash memory accesses and controls the SWE# input on the ROM. The pin floats whenever the bus is relinquished to an external device. 0 = write 1 = read
DEN#
1
O DATA ENABLE indicates data transfer cycles during a bus access. DEN# Sync(PB) is asserted at the start of the first data cycle and deasserted at the end of Rst(M) the last data cycle. The pin is used to provide control for data transceivers connected to the bus. The pin floats whenever the bus is relinquished to an external device O BURST LAST indicates the last data transfer of a bus access. BLAST# Sync(PB) remains active when wait states are inserted and becomes inactive after Rst(M) the final data transfer is complete. The pin floats whenever the bus is relinquished to an external device I/O READY / RECOVER During a data cycle the pin indicates that data can be Sync(PB) sampled or removed. Rst(M) 0 = sample data 1 = insert wait state During a recover state the pin indicates that the recover state is repeated. This function allows slow external devices longer to float their pins before the next address is driven. 0 = insert recovery state 1 = recovery complete
BLAST#
1
RDYRCV#
1
HOLD HOLDA
1 1
I HOLD is used by an external device to request access to the bus. Sync(PB) O HOLD ACKNOWLEDGE indicates to an external device that it has been Sync(PB) granted access to the bus. Rst(M) O Async PERIPHERAL BUS RESET indicates when the peripheral bus has been reset with P_RST# or a software reset.
PB_RST# PCE[5]# / PBI100MHZ# (Configuration Pin)
1 1
I/O PERIPHERAL CHIP ENABLES specify which of the six memory address Sync(PB) ranges are associated with the current bus access. The pin remains valid Rst(M) during the entire bus access. PERIPHERAL BUS 100 MHz ENABLE is latched at the deasserting edge of P_RST# and it indicates the speed at which the PBI bus operates. [PBI100MHZ#, PBI66MHZ#] 11= 33MHz 10 = 66MHz 01 = 100MHz 00 = Undefined (Default Mode) (Reserved - Do Not Use)
PCE[4]# / PBI66MHZ# (Configuration Pin)
1
I/O PERIPHERAL CHIP ENABLES specify which of the six memory address Sync(PB) ranges are associated with the current bus access. The pin remains valid Rst(M) during the entire bus access. PERIPHERAL BUS 66MHz ENABLE is latched at the deasserting edge of P_RST# and it indicates the speed at which the PBI bus operates. [PBI100MHZ#, PBI66MHZ#] 11= 33MHz 10 = 66MHz 01 = 100MHz 00 = Undefined (Default Mode) (Reserved - Do Not Use)
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June 2002
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Intel(R) 80321 I/O Processor Package Information
Table 4.
Peripheral Bus Interface Signals (Sheet 3 of 3)
Name PCE[3]# / P_BOOT16# (Configuration Pin) Count 1 Type Description
O PERIPHERAL CHIP ENABLES specify which of the six memory address Sync(PB) ranges are associated with the current bus access. The pin remains valid Rst(M) during the entire bus access. PERIPHERAL BUS BOOT WIDTH 16 ENABLE specifies the width of the peripheral bus for flash accesses during boot up. 0 = 16-bit bus width 1 = 8-bit bus width (Requires Pull-Down Resistor) (Default Mode)
PCE[2]# / 32BITPCI# (Configuration Pin)
1
I/O PERIPHERAL CHIP ENABLES specify which of the six memory address Sync(PB) ranges are associated with the current bus access. The pin remains valid Rst(M) during the entire bus access. 32 BIT PCI is latched at the deasserting edge of P_RST# and it indicates the width of the PCI-X bus to the PCI-X Status Register (bit 16 of the PCI-X Status Register). 0 = 32-Bit PCI-X Bus (Requires pull-down resistor) 1 = 64-Bit PCI-X Bus (Default mode)
PCE[1]# / RETRY (Configuration Pin)
1
PERIPHERAL CHIP ENABLES specify which of the six memory address I/O Sync(PB) ranges are associated with the current bus access. The pin remains valid Rst(M) during the entire bus access. RETRY is latched at the deasserting edge of P_RST# and it determines when the Primary PCI interface disables PCI configuration cycles by signaling a Retry until the Configuration Cycle Retry bit is cleared in the PCI Configuration and Status Register. 0 = Configuration Cycles enabled (Requires pull-down resistor) 1 = Retry enabled (Default mode)
PCE[0]# / RST_MODE# (Configuration Pin)
1
I/O PERIPHERAL CHIP ENABLES specify which of the six memory address Sync(PB) ranges are associated with the current bus access. The pin remains valid Rst(M) during the entire bus access. RESET MODE is latched at the deasserting edge of P_RST# and it determines when the 80321 is held in reset until the Intel(R) XScaleTM microprocessor Reset bit is cleared in the PCI Configuration and Status Register. 0 = Hold in reset (Requires pull-down resistor) 1 = Don't hold in reset (Default mode)
WIDTH[1:0]
2
O WIDTH denotes the physical memory attributes for a bus transaction. The Sync(PB) pins float whenever the bus is relinquished to an external device. Rst(M) 00 = 8 Bits Wide 01 = 16 Bits Wide 10 = 32 Bits Wide 11 = Reserved
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Intel(R) 80321 I/O Processor Package Information
Table 5.
PCI Bus Signals (Sheet 1 of 2)
Name P_AD[31:0] Count 32 Type I/O Sync(P) Rst(P) I/O Sync(P) Rst(P) I/O Sync(P) Rst(P) I/O Sync(P) Rst(P) I/O Sync(P) Rst(P) I/O Sync(P) Rst(P) O Rst(P) I/O Sync(P) Rst(P) I Sync(P) I/O Sync(P) Rst(P) I/O Sync(P) Rst(P) I/O Sync(P) Rst(P) I/O Sync(P) Rst(P) I/O Sync(P) Rst(P) I/O Sync(P) Rst(P) I/O OD Sync(P) Rst(P) I Description PCI ADDRESS/DATA is the multiplexed PCI address and bottom 32 bits of the data bus. PCI DATA is the upper 32 bits of the PCI data bus driven during the data phase. PCI BUS PARITY is even parity across P_AD[31:0] and P_C/BE[3:0]#.
P_AD[63:32]
32
P_PAR
1
P_PAR64
1
PCI BUS UPPER DWORD PARITY is even parity across P_AD[63:32] and P_C/BE[7:4]#. PCI BUS COMMAND and BYTE ENABLES are multiplexed on the same PCI pins. During the address phase, they define the bus command. During the data phase, they are used as byte enables for P_AD[31:0]. PCI BUS BYTE ENABLES are as byte enables for P_AD[63:32] during the data phase. PCI BUS REQUEST indicates to the PCI bus arbiter that the 80321 desires use of the PCI bus. PCI BUS REQUEST 64-BIT TRANSFER indicates the attempt of a 64-bit transaction on the PCI bus. When the target is 64-bit capable, the target acknowledges the attempt with the assertion of P_ACK64#. PCI BUS GRANT indicates that access to the PCI bus has been granted. PCI BUS ACKNOWLEDGE 64-BIT TRANSFER indicates that the device has positively decoded its address as the target of the current access and the target transfers data using the full 64-bit data bus. PCI BUS CYCLE FRAME is asserted to indicate the beginning and duration of an access. PCI BUS INITIATOR READY indicates the initiating agent's ability to complete the current data phase of the transaction. During a write, it indicates that valid data is present on the Address/Data bus. During a read, it indicates the processor is ready to accept the data. PCI BUS TARGET READY indicates the target agent's ability to complete the current data phase of the transaction. During a read, it indicates that valid data is present on the Address/Data bus. During a write, it indicates the target is ready to accept the data. PCI BUS STOP indicates a request to stop the current transaction on the PCI bus. PCI BUS DEVICE SELECT is driven by a target agent that has successfully decoded the address. As an input, it indicates whether or not an agent has been selected. PCI BUS SYSTEM ERROR is driven for address parity errors on the PCI bus.
P_C/BE[3:0]#
4
P_C/BE[7:4]#
4
P_REQ# P_REQ64#
1 1
P_GNT# P_ACK64#
1 1
P_FRAME#
1
P_IRDY#
1
P_TRDY#
1
P_STOP#
1
P_DEVSEL#
1
P_SERR#
1
P_CLK
1
PCI BUS INPUT CLOCK provides the timing for all PCI transactions and is the clock source for most internal 80321 units.
Datasheet
June 2002
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Intel(R) 80321 I/O Processor Package Information
Table 5.
PCI Bus Signals (Sheet 2 of 2)
Name P_RST# Count 1 Type I Async Description RESET brings PCI-specific registers, sequencers, and signals to a consistent state. When P_RST# is asserted: PCI output signals are driven to a known consistent state. PCI bus interface output signals are three-stated. Open drain signals such as P_SERR# are floated. P_RST# may be asynchronous to P_CLK when asserted or deasserted. Although asynchronous, deassertion must be guaranteed to be a clean, bounce-free edge. P_PERR# 1 I/O Sync(P) Rst(P) I Sync(P) O OD Async Rst(P) PCI BUS PARITY ERROR is asserted when a data parity error occurs during a PCI bus transaction. PCI BUS INITIALIZATION DEVICE SELECT is used to select the 80321 during a Configuration Read or Write command on the PCI bus. PCI BUS INTERRUPT requests an interrupt. The assertion and deassertion of P_INT[A:D]# is asynchronous to P_CLK. A device asserts its P_INT[A:D]# line when requesting attention from its device driver. Once the P_INT[A:D]# signal is asserted, it remains asserted until the device driver clears the pending request. P_INT[A:D]# Interrupts are level sensitive. PCI BUS 66 MHz ENABLE indicates the speed of the PCI bus. When this signal is sampled high the PCI bus speed is 66 MHz, when low the bus speed is 33 MHz.
P_IDSEL P_INT[A:D]#
1 4
P_M66EN
1
I
Table 6.
Serial Port Interface Signals
Name SSCKO SFRM Count 1 1 Type O Description SERIAL PORT CLOCK OUT is the output bit-rate clock.
O SERIAL FRAME indicates the beginning and end of a serial data word. Sync(SS) Rst(M) O TRANSMIT DATA is the outbound serial data pin. Sync(SS) Rst(M) I RECEIVE DATA is the inbound serial data pin. Sync(SS) I SERIAL PORT CLOCK IN is the input bit-rate clock which can be used when a frequency other than the default of 3.7 MHz is needed.
TXD
1
RXD SSCKI
1 1
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June 2002
Datasheet
Intel(R) 80321 I/O Processor Package Information
Table 7.
Miscellaneous Signals (Sheet 1 of 2)
Name XINT[3:0]# Count 4 Type I Async Description EXTERNAL INTERRUPT REQUESTS are used by external devices to request interrupt service. These pins are level-detect only and are internally synchronized. These interrupts can be directed to either the PCI pins P_INT[A:D]# or to the 80321 interrupt controller pins XINT[3:0]# as shown below. XINT[1]# XINT[2]# XINT[3]# HPI# 1 I Async I/O Async Rst(M) I/O Async Rst(P) I/O OD Rst(M) I/O Async Rst(P) I/O OD Rst(M) I/O Async Rst(P) I/O OD Rst(M) I/O Async Rst(P) I/O OD Rst(M) I Rst(T)
HIGH PRIORITY INTERRUPT causes a high priority non-maskable interrupt to the 80321. This pin is level-detect only and is internally synchronized. GENERAL PURPOSE INPUT/OUTPUT. These pins can be selected on a per pin basis as general purpose inputs or outputs. The default mode is a general purpose input. GENERAL PURPOSE INPUT/OUTPUT. These pins can be selected on a per pin basis as general purpose inputs or outputs. The default mode is a general purpose input. I2C DATA is used for data transfer and arbitration on the I2C bus. This is one of two I2C buses that the user can enable. GENERAL PURPOSE INPUT/OUTPUT. These pins can be selected on a per pin basis as general purpose inputs or outputs. The default mode is a general purpose input. I2C CLOCK provides synchronous operation of the I2C bus. This is one of two I2C buses that the user can enable. GENERAL PURPOSE INPUT/OUTPUT. These pins can be selected on a per pin basis as general purpose inputs or outputs. The default mode is a general purpose input. I2C DATA is used for data transfer and arbitration on the I2C bus. This is one of two I2C buses that the user can enable. GENERAL PURPOSE INPUT/OUTPUT. These pins can be selected on a per pin basis as general purpose inputs or outputs. The default mode is a general purpose input. I2C CLOCK provides synchronous operation of the I2C bus. This is one of two I2C buses that the user can enable. TEST CLOCK is an input which provides the clocking function for the IEEE 1149.1 Boundary Scan Testing (JTAG). State information and data are clocked into the component on the rising edge and data is clocked out of the component on the falling edge.
GPIO[3:0]
4
GPIO[4] / SDA1
1
GPIO[5] / SCL1
1
GPIO[6] / SDA0
1
GPIO[7] / SCL0
1
TCK
1
TDI
1
I TEST DATA INPUT is the serial input pin for the JTAG feature. TDI is Sync(T) sampled on the rising edge of TCK, during the SHIFT-IR and SHIFT-DR Rst(T) states of the Test Access Port. This signal has a weak internal pull-up to ensure proper operation when this signal is unconnected. O TEST DATA OUTPUT is the serial output pin for the JTAG feature. TDO is Sync(T)R driven on the falling edge of TCK during the SHIFT-IR and SHIFT-DR st(T) states of the Test Access Port. At other times, TDO floats. The behavior of TDO is independent of P_RST#. I Asyn Rst(T) TEST RESET asynchronously resets the Test Access Port (TAP) controller function of IEEE 1149.1 Boundary Scan Testing (JTAG). This signal has a weak internal pull-up.
TDO
1
TRST#
1
Datasheet
June 2002

XINT[0]#
P_INT[A]# or XINT[0]# P_INT[B]# or XINT[1]# P_INT[C]# or XINT[2]# P_INT[D]# or XINT[3]#
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Intel(R) 80321 I/O Processor Package Information
Table 7.
Miscellaneous Signals (Sheet 2 of 2)
Name TMS Count 1 Type I Sync(T) Rst(T) I Description TEST MODE SELECT is sampled at the rising edge of TCK to select the operation of the test logic for IEEE 1149.1 Boundary Scan testing. This signal has a weak internal pull-up to ensure proper operation when this signal is unconnected. RESISTER COMPENSATION is connected through a 30.1 1% 1/4 W resister to ground. This is used to minimize the PCI pin variations due to voltage and temperature variations. POWER FAIL DELAY is used with external delay circuits to delay the reset of the memory controller in a power-fail condition. This allows the self-refresh command to be sent to the DDR SDRAM array. POWER ON RESET should be tied to the 1.3 V supply. It is used to provide cloclks to the core from an internal ring oscillator during power up, which prevents internal contention. It also tristates the other pins to prevent external power sequencing contention. NO CONNECT pins have no usable function. However they are in the boundary scan chain and must not be connected to any signal, power or ground. PLL POWER is a separate VCC13 supply ball for the phase lock loop clock generator. It is to be connected to the board VCC13 plane. In noisy environments, add a simple bypass filter circuit to reduce noise-induced clock jitter and its effects on timing relationships. PLL POWER is a separate VCC13 supply ball for the phase lock loop clock generator. It is to be connected to the board VCC13 plane. In noisy environments, add a simple bypass filter circuit to reduce noise-induced clock jitter and its effects on timing relationships. 3.3 V POWER balls to be connected to a 3.3 V power board plane. 2.5 V POWER balls to be connected to a 2.5 V power board plane. 1.3 V POWER balls to be connected to a 1.3 V power board plane. GROUND balls to be connected to a ground board plane.
RCOMP
1
PWRDELAY
1
I Async I
POR#
1
NC[2:0]
3
I/O
VCCPLL1
1
PWR
VCCPLL2
1
PWR
V CC33 VCC25 VCC13 VSS
51 38 34 118
PWR PWR PWR GND
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June 2002
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Intel(R) 80321 I/O Processor Package Information
Table 8.
Pin Mode Behavior (Sheet 1 of 2)
Pin RCVENI# RCVENO# M_CK[2:0] M_CK[2:0]# M_RST# SA[12:0] SBA[1:0] SRAS# SCAS# SWE# SCE[1:0]# SCKE[1:0] DQ[63:32] Q[31:0] SCB[7:0] DQS[7:4] DQS[3:0] DQS[8] SDQM[7:4] SDQM[3:0] SDQM[8] AD[31:16] AD[15:8] AD[7:0] A[3:2] BE[3:0]# ALE ADS# PB_CLK W/R# FWE# DEN# BLAST# RDYRCV# HOLD HOLDA PB_RST# PCE[5]# / PBI100MHZ# PCE[4]# / PBI66MHZ# PCE[3]# / P_BOOT16# PCE[2]# / 32BITPCI# PCE[1]# / RETRY PCE[0]# / RST_MODE# WIDTH[1:0] Reset VI 1* VO VO 0 0* 0* 1* 1* 1* 1* 0* Z* Z* Z* Z* Z* Z* Z* Z* Z* 0 0 0 0 1 0 1 VO 0 1 1 1 VI VI VO 0 H H H H H H 0 Norm VI VO VO VO VO VO VO VO VO VO VO VO VB VB VB VB VB VB VO VO VO VB VB VB VO VO VO VO VO VO VO VO VO VI VI VO VO VO VO VO VO VO VO VO Hold Z Z Z Z Z Z Z Z Z Z Z 1 1 1 1 1 1 1 Z 32-Bit PCI 32-Bit Mem ID ID Z ECC Off ID ID Z -
Datasheet
June 2002
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Intel(R) 80321 I/O Processor Package Information
Table 8.
Pin Mode Behavior (Sheet 2 of 2)
Pin Reset Norm VB VB VB VB VB VB VB VO VB VI VB VB VB VB VB VB VB VI VI VB VI VO VI VO VO VO VI VI VI VI VB VB VB VB VI H VO H H VI H Hold 32-Bit PCI 32-Bit Mem ECC Off P_AD[63:32] Z P_AD[31:16] Z P_AD[15:0] Z P_PAR Z P_PAR64 Z P_C/BE[3:0]# Z P_C/BE[7:4]# Z P_REQ# Z P_REQ64# Z P_GNT# VI P_ACK64# Z P_FRAME# VI P_IRDY# VI P_TRDY# VI P_STOP# VI P_DEVSEL# VI P_SERR# Z P_CLK VI P_RST# VI P_PERR# Z P_IDSEL VI P_INT[A:D]# Z P_M66EN VI SSCKO VO SFRM VO TXD VO RXD VI SSCKI VI XINT[3:0]# VI HPI# VI GPIO[7] VI GPIO[6] VI GPIO[5] VI GPIO[4:0] VI TCK VI TDI H TDO Z TRST# H TMS H PWRDELAY VI NC[2:0] H NOTES: 1 = driven to VCC 0 = driven to VSS X = driven to unknown state ID = The input is disabled H = pulled up to VCC PD = pull-up disabled H H H NOTES:(continued) L = pulled down to VSS Z = output disabled (Floats) VB = acts like a Valid Bidirectional pin. VO = a Valid Output level is driven. VI = Need to drive a Valid Input level. * = After power fail sequence completes. ** = Caused by Hi-Z from mode pins only.
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Intel(R) 80321 I/O Processor Package Information
3.1.2
Figure 2.
544-Lead PBGA Package
544-Lead PBGA Package (Top View)
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June 2002
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Intel(R) 80321 I/O Processor Package Information
Figure 3.
544-Lead PBGA Package (Bottom View)
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Intel(R) 80321 I/O Processor Package Information
Figure 4.
Ball Map - Left Side - Top View
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June 2002
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Intel(R) 80321 I/O Processor Package Information
Figure 5.
Ball Map - Right Side - Top View
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Intel(R) 80321 I/O Processor Package Information
Table 9.
544-Lead PBGA Package - Alphabetical Ball Listing (Sheet 1 of 5)
Ball A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 Signal SA1 DQ35 DQ38 DQ34 DQ33 VREF SCB3 SDQM8 SCB0 SA2 DQ30 SDQM3 DQ28 SA8 DQ18 DQS2 DQ20 SCKE0 DQ14 DQS1 DQ8 DQ6 DQS0 DQ5 DQ0 AD31 SA0 DQ39 VSS DQS4 VSS RCVENO# V SS DQS8 VSS SA3 VSS DQ29 Ball B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 Signal VSS SA7 VSS DQ21 VSS SCKE1 VSS DQ13 VSS DQ2 VSS DQ4 V SS AD30 SA10 VSS VCC25 SDQM4 DQ36 VCC25 SCB7 SCB1 VCC25 SA4 DQ27 VCC25 DQ24 DQ23 VCC25 DQ17 SA9 VCC25 SDQM1 DQ12 VCC25 SDQM0 DQ1 VCC25 Ball C25 C26 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 Signal AD29 AD28 SRAS# SBA0 SBA1 VSS DQ37 DQ32 RCVENI# SCB2 SCB5 DQ31 DQ26 DQ25 SA6 DQ19 SDQM2 DQ16 SA11 DQ11 DQ15 DQ9 M_RST# DQ7 AD25 AD27 VSS AD26 DQ45 VSS DQ44 DQ40 VCC25 VSS SCB6 VSS SCB4 VSS
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Intel(R) 80321 I/O Processor Package Information
Table 9.
544-Lead PBGA Package - Alphabetical Ball Listing (Sheet 2 of 5)
Ball E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 Signal DQS3 VSS SA5 VSS DQ22 VSS SA12 VSS DQ10 VSS DQ3 VSS BE3# AD22 AD24 AD23 SDQM5 DQS5 VCC25 DQ41 VSS VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 BE2# Ball F23 F24 F25 F26 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 H1 H2 H3 H4 H5 H6 H7 H20 H21 H22 H23 H24 H25 H26 Signal AD21 VCC33 VSS AD20 DQ46 VSS DQ47 DQ43 DQ42 VCC25 VCC13 VCC13 VCC13 VCC13 VCC13 VCC13 VCC13 VCC13 VCC33 VSS BE1# AD17 AD19 AD18 DQ49 DQ48 SCAS# SWE# VSS VCC25 VCC13 VCC13 VCC33 WIDTH1 AD14 AD16 VSS AD15 Ball J1 J2 J3 J4 J5 J6 J7 J20 J21 J22 J23 J24 J25 J26 K1 K2 K3 K4 K5 K6 K7 K20 K21 K22 K23 K24 K25 K26 L1 L2 L3 L4 L5 L6 L11 L12 L13 L14 Signal DQS6 VSS VCC25 DQ53 DQ52 VCC25 VCC13 VCC13 VCC33 VSS AD11 VCC33 AD13 AD12 DQ50 DQ54 SDQM6 DQ55 VSS VCC25 VCC13 VCC13 VCC33 WIDTH0 AD8 AD10 VSS AD9 DQ60 VSS DQ51 SCE1# SCE0# VCC25 VSS VSS VSS VSS
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Intel(R) 80321 I/O Processor Package Information
Table 9.
544-Lead PBGA Package - Alphabetical Ball Listing (Sheet 3 of 5)
Ball L15 L16 L21 L22 L23 L24 L25 L26 M1 M2 M3 M4 M5 M6 M11 M12 M13 M14 M15 M16 M21 M22 M23 M24 M25 M26 N1 N2 N3 N4 N5 N6 N11 N12 N13 N14 N15 N16 Signal VSS V SS VCC33 V SS BE0# AD5 AD7 AD6 DQ57 DQ61 VCC25 DQ56 VSS VCC25 VSS VSS VSS VSS V SS V SS VCC13 A3 AD4 VCC33 VSS AD3 DQ62 V SS DQ58 SDQM7 DQS7 VCC25 VSS V SS V SS V SS V SS V SS Ball N21 N22 N23 N24 N25 N26 P1 P2 P3 P4 P5 P6 P11 P12 P13 P14 P15 P16 P21 P22 P23 P24 P25 P26 R1 R2 R3 R4 R5 R6 R11 R12 R13 R14 R15 R16 R21 R22 Signal VCC33 VSS A2 AD0 AD2 AD1 DQ59 M_CK2# M_CK2 DQ63 VSS VCC25 VSS VSS VSS VSS VSS VSS VCC13 FWE# W/R# ADS# VSS ALE M_CK1 V SS VCC25 M_CK0# M_CK0 VCC25 VSS VSS VSS VSS VSS VSS VCC33 VSS Ball R23 R24 R25 R26 T1 T2 T3 T4 T5 T6 T11 T12 T13 T14 T15 T16 T21 T22 T23 T24 T25 T26 U1 U2 U3 U4 U5 U6 U7 U20 U21 U22 U23 U24 U25 U26 V1 V2 Signal RDYRCV# VCC33 BLAST# DEN# M_CK1# P_INTB# P_INTA# RCOMP VSS VCC33 VSS VSS VSS VSS VSS VSS VCC13 PB_RST# HOLDA HOLD VSS PB_CLK P_INTD# VSS P_REQ# P_INTC# P_RST# VCC33 VCC13 VCC13 VCC33 VSS PCE5# PCE4# PCE3# PCE2# P_AD31 P_GNT#
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Intel(R) 80321 I/O Processor Package Information
Table 9.
544-Lead PBGA Package - Alphabetical Ball Listing (Sheet 4 of 5)
Ball V3 V4 V5 V6 V7 V20 V21 V22 V23 V24 V25 V26 W1 W2 W3 W4 W5 W6 W7 W20 W21 W22 W23 W24 W25 W26 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y17 Y18 Signal VCC33 P_AD30 VSS VCC33 VCC13 VCC13 VCC33 PCE0# NC0 VCC33 VSS PCE1# P_AD29 VSS P_AD27 P_AD28 P_AD26 VCC33 VCC13 VCC13 VCC33 VSS GPIO7 GPIO6 GPIO5 GPIO4 P_AD25 P_CBE3# P_AD24 P_IDSEL VSS VCC33 VCC13 VCC13 VCC13 VCC13 VCC13 VCC13 Ball Y19 Y20 Y21 Y22 Y23 Y24 Y25 Y26 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26 AB1 AB2 AB3 AB4 Signal VCC13 VCC13 VCC33 GPIO3 GPIO2 GPIO1 VSS GPIO0 P_AD23 VSS VCC33 P_AD22 P_AD20 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC13 VCC33 VCC13 VCC33 VCC13 VCC33 VCC33 VCC33 VCC33 VCC33 VSS SFRM VCC33 RXD TXD P_AD19 P_AD21 P_AD18 P_AD16 Ball AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 Signal VSS P_AD9 VSS P_AD$ VSS P_CBE7# VSS P_AD62 VSS P_AD54 VSS P_AD48 VSS P_AD40 VSS P_AD32 VSS VCC33 HPI# SSCKI VSS SSCKO P_AD17 VSS P_FRAME# P_TRDY# P_AD13 P_CBE0# P_CLK P_AD2 P_AD0 P_REQ64# P_PAR64 P_CBE4# P_AD58 P_AD56 P_AD52 P_AD50
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Intel(R) 80321 I/O Processor Package Information
Table 9.
544-Lead PBGA Package - Alphabetical Ball Listing (Sheet 5 of 5)
Ball AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 Signal P_AD44 P_AD42 P_AD36 P_AD34 TDO TRST# V SS XINT3# XINT2# XINT1# P_CBE2# P_STOP# VCC33 P_AD15 P_AD11 VCC33 P_AD6 P_M66EN VCC33 P_AD3 P_CBE5# VCC33 P_AD60 P_AD57 VCC33 P_AD49 P_AD46 VCC33 P_AD38 P_AD35 Ball AD21 AD22 AD23 AD24 AD25 AD26 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 Signal VCC33 TCK NC1 VCC33 VSS XINT0# P_IRDY# VSS P_PAR VSS P_AD14 V SS VCCPLL2 V SS P_AD7 VSS P_ACK64# VSS P_AD61 VSS P_AD53 VSS P_AD45 VSS P_AD39 VSS TDI VSS NC2 Ball AE24 AE25 AE26 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 Signal VSS VCC33 VCC33 P_DEVSEL# P_PERR# P_SERR# P_CBE1# VCCPLL1 P_AD12 P_AD10 P_AD8 P_AD5 P_AD1 P_CBE6# P_AD63 P_AD59 P_AD55 P_AD51 P_AD47 P_AD43 P_AD41 P_AD37 P_AD33 POR# TMS PWRDELAY VCC33 VCC33 VCC33
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Intel(R) 80321 I/O Processor Package Information
Table 10.
544-Lead PBGA Package - Alphabetical Signal Listing (Sheet 1 of 5)
Signal A2 A3 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 ADS# ALE BE0# BE1# Ball N23 M22 N24 N26 N25 M26 M23 L24 L26 L25 K23 K26 K24 J23 J26 J25 H23 H26 H24 G24 G26 G25 F26 F23 E24 E26 E25 D23 D26 D24 C26 C25 B26 A26 P24 P26 L23 G23 Signal BE2# BE3# BLAST# DEN# DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 Ball F22 E23 R25 R26 A25 C23 B22 E21 B24 A24 A22 D22 A21 D20 E19 D18 C20 B20 A19 D19 D16 C16 A15 D14 A17 B16 E15 C14 C13 D12 D11 C11 A13 B12 A11 D10 D6 A5 Signal DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 Ball A4 A2 C5 D5 A3 B2 E4 F4 G5 G4 E3 E1 G1 G3 H2 H1 K1 L3 J5 J4 K2 K4 M4 M1 N3 P1 L1 M2 N1 P4 A23 A20 A16 E11 B4 F2 J1 N5
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Intel(R) 80321 I/O Processor Package Information
Table 10.
544-Lead PBGA Package - Alphabetical Signal Listing (Sheet 2 of 5)
Signal DQS8 FWE# GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 HOLD HOLDA HPI# M_CK0 M_CK0# M_CK1 M_CK1# M_CK2 M_CK2# M_RST# NC0 NC1 NC2 P_ACK64# P_AD0 P_AD1 P_AD2 P_AD3 P_AD4 P_AD5 P_AD6 P_AD7 P_AD8 P_AD9 P_AD10 P_AD11 P_AD12 P_AD13 Ball B8 P22 Y26 Y24 Y23 Y22 W26 W25 W24 W23 T24 T23 AB23 R5 R4 R1 T1 P3 P2 D21 V23 AD23 AE23 AE11 AC9 AF10 AC8 AD10 AB8 AF9 AD7 AE9 AF8 AB6 AF7 AD5 AF6 AC5 Signal P_AD14 P_AD15 P_AD16 P_AD17 P_AD18 P_AD19 P_AD20 P_AD21 P_AD22 P_AD23 P_AD24 P_AD25 P_AD26 P_AD27 P_AD28 P_AD29 P_AD30 P_AD31 P_AD32 P_AD33 P_AD34 P_AD35 P_AD36 P_AD37 P_AD38 P_AD39 P_AD40 P_AD41 P_AD42 P_AD43 P_AD44 P_AD45 P_AD46 P_AD47 P_AD48 P_AD49 P_AD50 P_AD51 Ball AE5 AD4 AB4 AC1 AB3 AB1 AA5 AB2 AA4 AA1 Y3 Y1 W5 W3 W4 W1 V4 V1 AB20 AF20 AC20 AD20 AC19 AF19 AD19 AE19 AB18 AF18 AC18 AF17 AC17 AE17 AD17 AF16 AB16 AD16 AC16 AF15 Signal P_AD52 P_AD53 P_AD54 P_AD55 P_AD56 P_AD57 P_AD58 P_AD59 P_AD60 P_AD61 P_AD62 P_AD63 P_CBE0# P_CBE1# P_CBE2# P_CBE3# P_CBE4# P_CBE5# P_CBE6# P_CBE7# P_CLK P_DEVSEL# P_FRAME# P_GNT# P_IDSEL P_INTA# P_INTB# P_INTC# P_INTD# P_IRDY# P_M66EN P_PAR P_PAR64 P_PERR# P_REQ# P_REQ64# P_RST# P_SERR# Ball AC15 AE15 AB14 AF14 AC14 AD14 AC13 AF13 AD13 AE13 AB12 AF12 AC6 AF4 AD1 Y2 AC12 AD11 AF11 AB10 AC7 AF1 AC3 V2 Y4 T3 T2 U4 U1 AE1 AD8 AE3 AC11 AF2 U3 AC10 U5 AF3
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35
Intel(R) 80321 I/O Processor Package Information
Table 10.
544-Lead PBGA Package - Alphabetical Signal Listing (Sheet 3 of 5)
Signal P_STOP# P_TRDY# PB_CLK PB_RST# PCE0# PCE1# PCE2# PCE3# PCE4# PCE5# POR# PWRDELAY SRAS# RCOMP RCVENI# RCVENO# RDYRCV# RXD SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SBA0 SBA1 SCAS# SCB0 SCB1 SCB2 SCB3 Ball AD2 AC4 T26 T22 V22 V26 U26 U25 U24 U23 AF21 AF23 D1 T4 D7 B6 R23 AA25 B1 A1 A10 B10 C10 E13 D13 B14 A14 C17 C1 D17 E17 D2 D3 H3 A9 C8 D8 A7 Signal SCB4 SCB5 SCB6 SCB7 SCKE0 SCKE1 SCE0# SCE1# SDQM0 SDQM1 SDQM2 SDQM3 SDQM4 SDQM5 SDQM6 SDQM7 SDQM8 SFRM SSCKI SSCKO TCK TDI TDO TMS TRST# TXD VCC25 VCC13 VCC13 VCC13 VCC13 VCC13 VCC13 VCC13 VCC13 VCC13 VCC13 VCC13 Ball E9 D9 E7 C7 A18 B18 L5 L4 C22 C19 D15 A12 C4 F1 K3 N4 A8 AA23 AB24 AB26 AD22 AE21 AC21 AF22 AC22 AA26 F20 G7 G8 G9 G10 G17 G18 G19 G20 H7 H20 J7 Signal VCC13 VCC13 VCC13 VCC13 VCC13 VCC13 VCC13 VCC13 VCC13 VCC13 VCC13 VCC13 VCC13 VCC13 VCC13 VCC13 VCC13 VCC13 VCC13 VCC13 VCC13 VCC13 VCC13 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 Ball J20 K7 K20 U7 U20 V7 W7 W20 Y7 Y8 Y9 Y10 Y17 Y19 Y20 M21 P21 T21 V20 Y18 AA12 AA14 AA16 C3 C6 C9 C12 C15 C18 C21 C24 E5 F3 F6 F7 F8 F9 F10
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Intel(R) 80321 I/O Processor Package Information
Table 10.
544-Lead PBGA Package - Alphabetical Signal Listing (Sheet 4 of 5)
Signal VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 Ball F11 F12 F13 F14 F15 F16 F17 F18 F19 F21 G6 H6 J3 J6 K6 L6 M3 M6 N6 P6 R3 R6 F24 G21 H21 J21 J24 K21 L21 M24 N21 R21 R24 U21 V21 V24 W21 Y21 Signal VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCCPLL1 VCCPLL2 VREF Ball AA21 AA24 AB22 AD24 AA3 AA6 AA7 AA8 AA9 AA10 AA11 AA13 AA15 AA17 AA18 AA19 AA20 AD3 AD6 AD9 AD12 AD15 AD18 AD21 AE25 AE26 AF24 AF25 AF26 T6 U6 V3 V6 W6 Y6 AF5 AE7 A6 Signal VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball B3 B5 B7 B9 B11 B13 B15 B17 B19 B21 B23 B25 C2 D25 D4 E2 E6 E8 E10 E12 E14 E16 E18 E20 E22 F5 F25 G2 G22 H5 H25 J2 J22 K5 K25 L2 L11 L12
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Intel(R) 80321 I/O Processor Package Information
Table 10.
544-Lead PBGA Package - Alphabetical Signal Listing (Sheet 5 of 5)
Signal VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball L13 L14 L15 L16 L22 M5 M11 M12 M13 M14 M15 M16 M25 N2 N11 N12 N13 N14 N15 N16 N22 P5 P11 P12 P13 P14 P15 P16 P25 R2 Signal VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball R11 R12 R13 R14 R15 R16 R22 T5 T11 T12 T13 T14 T15 T16 T25 U2 U22 V5 V25 W2 W22 Y5 Y25 AA2 AA22 AB5 AB7 AB9 AB11 AB13 Signal VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS SWE# WIDTH00 WIDTH01 W/R# XINT0# XINT1# XINT2# XINT3# Ball AB15 AB17 AB19 AB21 AB25 AC2 AC23 AD25 AE2 AE4 AE6 AE8 AE10 AE12 AE14 AE16 AE18 AE20 AE22 AE24 H4 K22 H22 P23 AD26 AC26 AC25 AC24
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Intel(R) 80321 I/O Processor Package Information
3.2
Package Thermal Specifications
The device is specified for operation when TC (case temperature) is within the range of 0C to 105C, depending on operating conditions. Refer to the "Thermal Data for the 544-lead PBGA package" application note for more information regarding maximum case temperatures on the 544-lead PBGA package. Case temperature may be measured in any environment to determine whether the processor is within specified operating range. Measure the case temperature at the center of the top surface, opposite the ballpad.
3.2.1
Thermal Specifications
This section defines the terms used for thermal analysis.
3.2.1.1
Ambient Temperature
Ambient temperature, TA, is the temperature of the ambient air surrounding the package. In a system environment, ambient temperature is the temperature of the air upstream from the package.
3.2.1.2
Case Temperature
When measuring case temperature, attention to detail is required to ensure accuracy. When a thermocouple is used, calibrate it before taking measurements. Errors may result when the measured surface temperature is affected by the surrounding ambient air temperature. Such errors may be due to a poor thermal contact between thermocouple junction and the surface, heat loss by radiation, or conduction through thermocouple leads. To minimize measurement errors:
* Use a 35 gauge K-type thermocouple or equivalent. * Attach the thermocouple bead or junction to the package top surface at a location
corresponding to the center of the die (Figure 6). The center of the die gives a more accurate measurement and less variation as the boundary condition changes.
* Attach the thermocouple bead at a 0 angle with respect to the package as shown in Figure 6,
when no heatsink is attached. Figure 6. Thermocouple Attachment - No Heatsink
Intel(R) 80321
I/O Processor
Thermocouple
3.2.1.3
Thermal Resistance
The thermal resistance value for the case-to-ambient, CA, is used as a measure of the cooling solution's thermal performance.
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Intel(R) 80321 I/O Processor Package Information
3.2.2
Thermal Analysis
Table 11 lists the case-to-ambient thermal resistances of the 80321 for different air flow rates with and without a heat sink. To calculate TA, the maximum ambient temperature to conform to a particular case temperature: TA = TC - P (CA) Compute P by multiplying ICC and VCC. Values for JC and CA are given in Table 11. Junction temperature (TJ) is commonly used in reliability calculations. TJ can be calculated from JC (thermal resistance from junction to case) using the following equation: TJ = TC + P (JC) Similarly, when TA is known, the corresponding case temperature (TC) can be calculated as follows: TC = TA + P (CA) The JA (Junction to Ambient) for this package is currently estimated at 16.87 C/Watt with no airflow and no heatsink. JA = JC + CA
Table 11.
544-Lead PBGA Package Thermal Characteristics
Thermal Resistance -- C/Watt Airflow -- ft/min (m/sec) Parameter JC (Junction-to-Case) CA (Case-to-Ambient) Without Heatsink 0 (0) 1.00 15.87 50 (0.25) 1.00 14.72 JA 100 (0.50) 1.00 13.99 200 (1.01) 1.00 12.94 300 (1.52) 1.00 12.20 400 (2.03) 1.00 11.73 600 (3.04) 1.00 10.90 800 (4.06) 1.00 10.39
JC
CA
NOTES: 1. This table applies to a H-PBGA device soldered directly onto a board. 2. Estimated value.
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Intel(R) 80321 I/O Processor Package Information
3.3
Socket Information
Table 12 and Table 13 provide vendor details for socket-headers and burn-in sockets for the 80321. This is neither an endorsement nor a warranty of the performance of any of the listed products and/or companies.
3.3.1
Table 12.
Socket-Header Vendor
Socket-Header Vendor
Part # Company Factory Representative John Miller Phone/Fax # BGA 544-Pin Header TBD BGA 544-Pin Socket Carrier TBD
Adapter Technologies 214-218 South 4th Street Perkasie, PA 18944
215 258-5750 215 258-5760
3.3.2
Table 13.
Burn-in Socket Vendor
Burn-in Socket Vendor
Company Yamaichi 2235 Zanker Road San Jose, CA 95131 Factory Representative Steve Drake Phone # TBD Burn-in Socket Part # NP276-67613. AC-14847
3.3.3
Table 14.
Shipping Tray Vendor
Shipping Tray Vendor
Company Daewon Semiconductor Factory Representative Sunna Chung Phone # 82.31.794.2001 Shipping Tray Part # 127-3535-919, Rev. D
3.3.4
Table 15.
Logic Analyzer Interposer Vendor
Logic Analyzer Interposer Vendor
Company Delphi Connection Systems 17150 Von Kaman Avenue Irvine, CA 92614-0968 Factory Representative Bob Betz Phone/Fax # 949 660-6968 949 660-5825 TBD Part #
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Intel(R) 80321 I/O Processor Package Information
3.3.5
Table 16.
JTAG Emulator Vendor
JTAG Emulator Vendor
Company ARM, Ltd. www.arm.com WindRiver HSI www.windriver.com Part # Multi-ICE Interface Unit ARM KP1-0019A visionPROBE/visionICE for Intel(R) XScaleTM microarchitecture
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Intel(R) 80321 I/O Processor Electrical Specifications
4.0
4.1
Electrical Specifications
Absolute Maximum Ratings
Parameter Storage Temperature Case Temperature Under Bias Maximum Rating -55C to +125C 0C to +105C NOTICE: This data sheet contains information on products in the design phase of development. Do not finalize a design with this information. Revised information will be published when the product becomes available. The specifications are subject to change without notice. Contact your local Intel representative before finalizing a design.
Supply Voltage VCC33 wrt. VSS -0.5V to +4.1V Supply Voltage VCC25 wrt. VSS -0.5V to +3.6V Supply Voltage VCC13 wrt. VSS -0.5V to +2.1V Voltage on Any Ball wrt. VSS -0.5V to VCCP + 0.5V
WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.
Table 17.
Operating Conditions
Symbol VCC33 VCC25 VCC13 VCCPLL1 VCCPLL2 VREF FP_CLK TC Parameter 3.3V PCI Supply Voltage 2.5V DDR Supply Voltage 1.3V CORE Supply Voltage PLL Supply Voltage PLL Supply Voltage Memory I/O Reference Voltage Input Clock Frequency Case Temperature Under Bias Min 3.0 2.3 1.235 VCC13 VCC13 16 0 Max 3.6 2.7 1.365 VCC13 VCC13 133 105 Units V V V V V V MHz C Notes
V CC25 /2 - 0.05 V CC25 /2 + 0.05
4.2
VCCPLL Pin Requirements
To reduce clock skew, the VCCPLL1, VCCPLL2, VSSPLL1 and VSSPLL2 balls for the Phase Lock Loop (PLL) circuit are isolated on the package. The lowpass filter, as shown in Figure 7, reduces noise induced clock jitter and its effects on timing relationships in system designs. The 4.7 F capacitor must be (low ESR solid tantalum), the 0.01 F capacitor must be of the type X7R and the node connecting VCCPLL must be as short as possible. The VSSPLL balls should be connected to the board ground plane.
Figure 7.
VCCP L L Lowpass Filter
+ 4.7F 0.01F VCCPLL
VCC13 (Board Plane)
10, 5%, 1/8W
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Intel(R) 80321 I/O Processor Electrical Specifications
4.3
Table 18.
Targeted DC Specifications
DC Characteristics
Symbol VIL1 V IH1 V IL2 VIH2 V IL3 V IH3 V IL4 V OL1 V OH1 V OL2 V OH2 V OL3 V OH3 C IN C CLK LPIN Parameter Input Low Voltage (SDRAM) Input High Voltage (SDRAM) Input Low Voltage (Misc.) Input High Voltage (Misc.) Input Low Voltage (PCI-X) Input High Voltage (PCI-X/PCI) Input Low Voltage (PCI) Output Low Voltage (Misc.) Output High Voltage (Misc.) Output Low Voltage (SDRAM) Output High Voltage (SDRAM) Output Low Voltage (PCI-X) Output HIGH Voltage (PCI-X) Input pin Capacitance Clock pin Capacitance Ball Inductance 5 0.9 VCC33 8 8 15 1.95 0.1 VCC33 2.4 0.35 Min -0.3 VREF + 0.15 -0.3 2.0 -0.5 0.5 VCC33 -0.5 Max VREF - 0.15 VCC25 + 0.3 0.8 VCC33 + 0.3 0.35 VCC33 VCC33 + 0.5 0.3 VCC33 0.4 Units V V V V V V V V V V V V V pF pF nH (3,5) (3,5) (4) (4) (1) (1) (1) IOL = 6 mA (4) IOH = -2 mA (4) IOL = 15.2 mA (3,5) IOH = -15.2 mA (3,5) IOL = 1500 A(1) IOH = -500 A(1) (1, 2) (1, 2) (1,2) Notes
NOTES: 1. As required by the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a. 2. Not tested. 3. SDRAM signals include MA[12:0], BA[1:0], CAS#, CS[1:0]#, CKE[1:0], DM[8:0], RAS#, WE#, RCVENI#, RCVENO#, M_CK[2:0], M_CK[2:0]#, DQ[63:0], DQS[8:0] and CB[7:0]. 4. Miscellaneous signals include all signals that are not PCI or SDRAM signals. 5. Only 2.5V DDR SDRAM is supported.
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Intel(R) 80321 I/O Processor Electrical Specifications
Table 19.
ICC Characteristics
Symbol ILI1 ILI2 Parameter Input Leakage Current for each signal except TCK, TMS, TRST#, TDI Input Leakage Current for TCK, TMS, TRST#, TDI -140 Typ Max 2 -250 0.6 0.5 1.3 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Units A A A A A A A A A A A Notes 0 VIN VCC (5) VIN = 0.45 V (1,5) (1,2) (1,2) (1,2) (1,3) (1,3) (1,3) (4) (4) (4) (4) (4) (4)
Power Supply Current ICC33 Active (Power Supply) Power Supply Current ICC25 Active (Power Supply) Power Supply Current ICC13 Active (Power Supply) ICC33 Active (Thermal) ICC25 Active (Thermal) ICC13 Active (Thermal) Thermal Current Thermal Current Thermal Current
Reset Mode ICC33 Active (Power Modes) Hi-Z Mode Reset Mode ICC25 Active (Power Modes) Hi-Z Mode Reset Mode ICC13 Active (Power Modes) Hi-Z Mode
NOTES: 1. Measured with device operating and outputs loaded to the test condition in Figure 14. 2. ICC Active (Power Supply) value is provided for selecting your system's power supply. It is measured using one of the worst case instruction mixes with VCC33 = 3.6V, VCC25 = 2.7V, VCC13 = 1.365V and ambient temperature = 55 C. 3. ICC Active (Thermal) value is provided for your system's thermal management. Typical ICC is measured with VCC33 = 3.3V, VCC25 = 2.5V, VCC13 = 1.3V and ambient temperature = 55 C. 4. ICC Test (Power modes) refers to the ICC values that are tested when the device is in Reset mode or ONCE mode with VCC33 = 3.6V, VCC25 = 2.7V, VCC13 = 1.4Vand ambient temperature = 55 C. 5. Input leakage currents include hi-Z output leakage for all bi-directional buffers with tri-state outputs.
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Intel(R) 80321 I/O Processor Electrical Specifications
4.4
4.4.1
Table 20.
Targeted AC Specifications
Clock Signal Timings
Clock Timings
PCI-X 133 PCI-X 100 Symbol TF1 TC1 TCH1 TCL1 TSR1 Parameter Min Max Min Max Min Max Min Max Min Max PCI clock Frequency PCI clock Cycle Time PCI clock High Time PCI clock Low Time PCI clock Slew Rate 100 7.5 3 3 1.5 4 133 10 66 10 3 3 1.5 4 100 15 50 15 6 6 1.5 4 66 20 33 15 6 6 1.5 4 66 30 16 30 11 11 1 4 33 60 MHz ns ns ns V/ns 2 1 1, 3 PCI-X 66 PCI 66 PCI 33 Units Notes
Spread Spectrum Requirements fmod fspread PCI clock modulation frequency PCI clock frequency spread 30 -1 33 0 30 -1 33 0 30 -1 33 0 30 -1 33 0 PC200 Symbol TF2 TC2 TCH2 TCL2 TCS2 Tskew2 Symbol TF3 TC3 TCH3 TCL3 TCS3 Parameter Min DDR SDRAM clock Frequency DDR SDRAM clock Cycle Time DDR SDRAM clock High Time DDR SDRAM clock Low Time DDR SDRAM clock Period Stability DDR SDRAM clock skew for M_CK[2:0] and M_CK[2:0]# PBI 100 Parameter Min Max Min Max Min Max PBI clock Frequency PBI clock Cycle Time PBI clock High Time PBI clock Low Time PBI clock Period Stability 10 3 3
90
KHz %
Units Notes Max 100 10 4.5 4.5 5.5 5.5
90
MHz ns ns ns ps ps Units Notes
200 PBI 66 PBI 33
100 15 6 6
66 30 11 11
90
33
MHz ns ns ns
90
ps
NOTES: 1. The clock frequency may not change beyond the spread-spectrum limits except while P_RST# is asserted. 2. This slew rate must be met across the minimum peak-to-peak portion of the clock waveform. 3. The minimum clock period must not be violated for any single clock cycle, i.e., accounting for all system jitter.
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4.4.2
Table 21.
PCI Interface Signal Timings
PCI Signal Timings
Symbol Parameter PCI-X 133 PCI-X 100 PCI-X 66 PCI 66 PCI 33 Units Notes
Min Max Min Max Min Max Min Max TOV1 TOV2 TOF TIS1 TIS2 TIH1 TRST TRF TIS3 TIH2 TIS4 TIH3 Clock to Output Valid Delay for bused signals Clock to Output Valid Delay for point to point signals Clock to Output Float Delay Input Setup to clock for bused signals Input Setup to clock for point to point signals Input Hold time from clock Reset Active Time Reset Active to output float delay REQ64# to Reset setup time Reset to REQ64# hold time PCI-X initialization pattern to Reset setup time Reset to PCI-X initialization pattern hold time 10 0 10 0 50 50 1.2 1.2 0.5 1 40 10 0 10 0 50 50 0.7 0.7 3.8 3.8 7 1.7 1.7 0.5 1 40 10 0 50 0.7 0.7 3.8 3.8 7 3 5 0 1 40 10 0 50 1 2 6 6 14 7 10, 12 0 1 40 2 2 11 12 28 ns ns ns ns ns ns ms ns clocks ns clocks ns 5, 6 1, 2, 3 1, 2, 3 1, 7 3, 4, 8 3, 4 4
NOTES: 1. See the timing measurement conditions in Figure 9 "Output Timing Measurement Waveforms" on page 51. 2. See Figure 15 "PCI/PCI-X TOV(max) Rising Edge AC Test Load" on page 55, Figure 16 "PCI/PCI-X TOV(max) Falling Edge AC Test Load" on page 55 and Figure 17 "PCI/PCI-X TOV(min) AC Test Load" on page 56. 3. Setup time for point-to-point signals applies to REQ# and GNT# only. All other signals are bused. 4. See the timing measurement conditions in Figure 10 "Input Timing Measurement Waveforms" on page 52. 5. RST# is asserted and deasserted asynchronously with respect to CLK. 6. All output drivers must be floated when RST# is active. 7. For purposes of Active/Float timing measurements, the HI-Z or "off" state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 8. Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at the same time.
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Intel(R) 80321 I/O Processor Electrical Specifications
4.4.3
Table 22.
DDR SDRAM Interface Signal Timings
DDR SDRAM Signal Timings
Symbol TVB1 TVA1 TVB2 TVA2 TVB3 TVA3 TVB4 TVA4 TVB5 TVA5 TVB6 Parameter DQ, CB and DM output valid time before associated DQS DQ, CB and DM output valid time after associated DQS DQS output valid time before CK DQS output valid time after CK Address and Control write output valid before CK Address and Control write output valid after CK DQS read input valid time before DQ DQS read input valid time after DQ RCVENO# output valid time before CK RCVENO# output valid time after CK RCVENI# input valid time before DQS 3.0 4.2 3.5 1.6 1.6 1.4 1.0 Min 1.3 1.3 1.4 1.0 Max Units ns ns ns ns ns ns ns ns ns ns ns Notes 4 4 4 4 4 4 5 5 5 5 5
NOTES: 1. See Figure 9 "Output Timing Measurement Waveforms" on page 51. 2. See Figure 10 "Input Timing Measurement Waveforms" on page 52. 3. These output valid times are specified with a 0 pF loading. 4. See Figure 12 "DDR SDRAM Write Timings" on page 53. 5. See Figure 13 "DDR SDRAM Read Timings" on page 54.
4.4.4
Table 23.
Peripheral Bus Interface Signal Timings
Peripheral Bus Signal Timings
Sym TOV1 TOF TIS1 TIH1 Parameter Output Valid Delay from PB_CLK Output Float Delay from PB_CLK Input Setup to PB_CLK Input Hold from PB_CLK Min 1 1 4.9 2 Max 5.5 5.5 Units ns ns ns ns Notes (1,3) (1,3) (2) (2)
NOTES: 1. See Figure 9 "Output Timing Measurement Waveforms" on page 51. 2. See Figure 10 "Input Timing Measurement Waveforms" on page 52. 3. See Figure 14 "AC Test Load for all Signals Except PCI and DDR SDRAM" on page 55.
4.4.5
Table 24.
I2C Interface Signal Timings
I2C Signal Timings (Sheet 1 of 2)
Std. Mode Symbol FSCL TBUF Parameter Min SCL Clock Frequency Bus Free Time Between STOP and START Condition 0 4.7 Max 100 Min 0 1.3 Max 400 KHz s (1) Fast Mode Units Notes
NOTES: 1. See Figure 11 "I2C Interface Signal Timings" on page 52. 2. Not tested. 3. After this period, the first clock pulse is generated. 4. Cb = the total capacitance of one bus line, in pF.
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Table 24.
I2C Signal Timings (Sheet 2 of 2)
Std. Mode Symbol THDSTA TLOW THIGH TSUSTA THDDAT TSUDAT TSR TSF TSUSTO Parameter Min Hold Time (repeated) START Condition SCL Clock Low Time SCL Clock High Time Setup Time for a Repeated START Condition Data Hold Time Data Setup Time SCL and SDA Rise Time SCL and SDA Fall Time Setup Time for STOP Condition 4 4 4.7 4 4.7 0 250 1000 300 3.45 Max Min 0.6 1.3 0.6 0.6 0 100 20+0.1Cb 20+0.1Cb 0.6 300 300 0.9 Max s s s s s ns ns ns s (1,3) (1,2) (1,2) (1) (1) (1) (1,4) (1,4) (1) Fast Mode Units Notes
NOTES: 1. See Figure 11 "I2C Interface Signal Timings" on page 52. 2. Not tested. 3. After this period, the first clock pulse is generated. 4. Cb = the total capacitance of one bus line, in pF.
4.4.6
Table 25.
SSP Interface Signal Timings
SSP Signal Timings
Symbol TIS TIH TOV TOV Input Setup to SSCKO Input Hold from SSCKO Output Valid Delay from SSCKO Output Valid Delay from SSCKI to SSCKO in external clock mode. Parameter Min 9 0 -1 3 2 10 Max Units ns ns ns ns Notes
Datasheet
June 2002
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Intel(R) 80321 I/O Processor Electrical Specifications
4.4.7
Table 26.
Boundary Scan Test Signal Timings
Boundary Scan Test Signal Timings
Symbol TBSF TBSCH TBSCL TBSCR TBSCF TBSIS1 TBSIH1 TBSOV1 TOF1 Parameter TCK Frequency TCK High Time TCK Low Time TCK Rise Time TCK Fall Time Input Setup to TCK Input Hold from TCK TDO Output Valid Delay from falling edge of TCK. TDO Output Float Delay from falling edge of TCK. 3 3 1 1 11 11 Min 0 7.5 7.5 5 5 Max 66 Units MHz ns ns ns ns ns ns ns ns Measured at 1.5 V (1) Measured at 1.5 V (1) 0.8 V to 2.0 V (1) 2.0 V to 0.8 V (1) (4) (4) (2, 3) (2, 5) Notes
NOTES: 1. Not tested. 2. Outputs precharged to VCC5. 3. See Figure 9 "Output Timing Measurement Waveforms" on page 51. 4. See Figure 10 "Input Timing Measurement Waveforms" on page 52. 5. A float condition occurs when the output current becomes less than ILO. Float delay is not tested. See Figure 9 "Output Timing Measurement Waveforms" on page 51.
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June 2002
Datasheet
Intel(R) 80321 I/O Processor Electrical Specifications
4.5
Figure 8.
AC Timing Waveforms
Clock Timing Measurement Waveforms
TCR Vih(min) Vil(max) TCH TCL TC TCF Vtch Vtest Vtcl
Figure 9.
Output Timing Measurement Waveforms
Vth CLK Vtest Vtl TOV
OUTPUT DELAY FALL
Vtfall
TOV
OUTPUT DELAY RISE
Vtrise
TOF OUTPUT FLOAT
Datasheet
June 2002
51
Intel(R) 80321 I/O Processor Electrical Specifications
Figure 10.
Input Timing Measurement Waveforms
Vth CLK Vtest TIH Vtl
TIS
Vth INPUT Vtest Valid Vtest Vmax Vtl
Figure 11.
I2C Interface Signal Timings
SDA TBUF TLOW TSR TSF THDSTA TSP
SCL THDSTA Stop Start THDDAT THIGH TSUDAT TSUSTA Repeated Start TSUSTO Stop
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June 2002
Datasheet
Intel(R) 80321 I/O Processor Electrical Specifications
Figure 12.
DDR SDRAM Write Timings
ADDR/CTRL
TVB3
TVA3
CK TVB2 TVA2
DQS
TVB1
TVA1
DQ
Datasheet
June 2002
53
Intel(R) 80321 I/O Processor Electrical Specifications
Figure 13.
DDR SDRAM Read Timings
CK TVA5 rcveno# TVB5
rcveni#
TVB6 DQS TVB4 TVA4 DQ
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June 2002
Datasheet
Intel(R) 80321 I/O Processor Electrical Specifications
4.6
Table 29.
AC Test Conditions
AC Measurement Conditions
Symbol Vtch V tcl Vth Vtl Vtest Vtrise Vtfall Vmax Slew Rate PCI-X 0.6 VCC33 0.2 VCC33 0.6 VCC33 0.25 VCC33 0.4 VCC33 0.285 VCC33 0.615 VCC33 0.4 VCC33 1.5 PCI 0.6 VCC33 0.2 VCC33 0.6 VCC33 0.2 VCC33 0.4 VCC33 0.285 VCC33 0.615 VCC33 0.4 VCC33 1.5 DDR 2.0 0.5 1.25 1.25 1.25 1.5 1.5 PBI 2.0 0.8 1.5 1.5 1.5 1.2 1.5 Units V V V V V V V V V/nS 1 Notes
1. Input signal slew rate is measured between Vil and Vih.
Figure 14.
AC Test Load for all Signals Except PCI and DDR SDRAM
Test Point Output 50pF
Figure 15.
PCI/PCI-X TOV(max) Rising Edge AC Test Load
Test Point Output 25 10pF
Figure 16.
PCI/PCI-X TOV(max) Falling Edge AC Test Load
VCC33 25 Output 10pF Test Point
Datasheet
June 2002
55
Intel(R) 80321 I/O Processor Electrical Specifications
Figure 17.
PCI/PCI-X TOV(min) AC Test Load
VCC33 1K Output 1K 10pF Test Point
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June 2002
Datasheet

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